In a dynamic memory device, an electric potential of a semiconductor substrate is required to be lower than a reference potential or a ground potential for the purposes of reducing a sub-threshold leakage current in a cell transistor and preventing the so-called latch-up phenomenon. To this end, a charge pumping circuit is generally employed to generate and supply such a potential to the substrate. A substrate potential detection circuit is further provided to control the charge pumping circuit, as disclosed in Japanese Patent Application (Kokai) Hei 5-54650.
In this prior art technique, the substrate potential detection circuit detects the substrate potential and controls the charge pumping circuit such that the charge pumping circuit is activated if the substrate potential is detected to be higher than a predetermined level (hereafter called "pre-set level") and deactivated if the substrate potential is lower than the pre-set level. The substrate potential is thus maintained at the pro-set level.
Referring to FIG. 4, the substrate potential detection circuit of the prior art comprises a P-channel MOS transistors Q6 and Q7 connected in series between a reference voltage line VREF and a ground line GND to divide the reference voltage VREF and supply a divided voltage to a node D. The transistor Q8 has a gate connected to GND and the transistor Q7 has a gate applied with a substrate potential VBB which is supplied to a semiconductor substrate (not shown). In addition, a P-channel MOS transistor Q8 with a gate connected to the node D, an N-channel MOS transistor Q9 with a gate connected to the reference voltage VREF and an inverter 10, which are connected as shown, constitute a buffer outputting a substrate detection signal EBBG. The reference voltage VREF is kept constant irrespective of a power supply voltage VCC.
The detection signal EBBG is employed to activate and deactivate a charge pumping circuit (not shown). That is, the charge pumping circuit is activated when the logic level of the output EBBG value is "1" and deactivated when the signal EGGB is at "0". The logic level of the output EBBG is in turn determined by the ratio of the current drive capability of the transistor Q8 to that of the transistor Q9. The current drive capability of the transistor Q8 is dependent on the source-gate voltage V.sub.CS of the transistor Q8.
More specifically, since the N-channel transistor Q9 is so arranged as to have a relatively small current capability, the potential at a node E is pulled approximately up to VREF level when the source-gate voltage V.sub.CS of the P-channel transistor Q8 is greater than a threshold voltage .vertline.V.sub.TP .vertline. of the transistor Q8 by a small level .alpha. (ex. .alpha. is 100 to 200 mV). As a result thereof, as shown in FIG. 5, the output signal EBBG is set to "1" and "0" when the source-gate voltage .vertline.V.sub.CS .vertline. of the transistor Q8 is .vertline.V.sub.CS .vertline.&lt;.vertline.V.sub.TP .vertline.+.alpha. and .vertline.V.sub.CS .vertline..ltoreq..vertline.V.sub.TP .vertline.+.alpha., respectively.
By adjusting a ratio of channel width W of the transistor Q6 to that of the transistor Q7, the source-gate voltage .vertline.V.sub.CS .vertline. of the transistor Q8 may be set to satisfy the following equation when the substrate potential VBB is at the pre-set level, EQU .vertline.V.sub.CS .vertline.=VREF-VD=.vertline.V.sub.TP .vertline.+.alpha.
where VD denotes the electric potential at the voltage dividing node D.
If the substrate potential VBB becomes higher than the pre-set level, the current flowing through the transistor Q7 is decreased so that the potential VD at the node D is increased. The reason is that the transistor Q6 operates as a resistive element so that the voltage drop thereacross is enlarged by the increase of the current flowing through the transistor Q6. As a result, the P-channel transistor Q8 is rendered non-conductive when the source-gate voltage of the transistor Q8 becomes smaller than .vertline.V.sub.TP .vertline.+.alpha.. Since the N-channel transistor Q9 is in a conductive state, the potential at the output node E is lowered to the ground level to switch the output EBBG from "0" to "1" for activating the charge pumping circuit.
On the other hand, if the reference potential VBB level is lower than the pre-set level, the current flowing through the transistor Q7 is increased. As a result, the potential VD at the voltage dividing node D is lowered so that the source-gate voltage of the transistor Q8 is made to satisfy the condition of .vertline.V.sub.CS .vertline.&gt;.vertline.V.sub.TP .vertline.+.alpha. the transistor Q8 being thereby brought into a conductive state. The potential at the output node E is thus pulled up to the VREF level to switch the output EBBG from "1" to "0" for deactivating the charge pumping circuit.
The above-described conventional substrate potential detection circuit is constructed such that the potential at the node D is dependent on the substrate potential VBB to determine the activation and deactivation of the charge pumping circuit when the source-gate voltage .vertline.V.sub.CS .vertline. of the transistor Q8 is .vertline.V.sub.CS .vertline.&lt;.vertline.V.sub.TP .vertline.+.alpha. and .vertline.VG.sub.s .vertline.&lt;.vertline.V.sub.TP .vertline.+.alpha., respectively.
As a result, the detection level of the substrate potential VBB is directly affected by the fluctuation in the threshold voltage .vertline.V.sub.TP .vertline. of the transistor Q8 caused by the fluctuation in the manufacturing process.
Referring to FIG. 6 and FIG. 7, the above-mentioned problems will be explained in detail. The characteristic curve shown in FIG. 6 indicates the dependence of the ON resistance of the transistor Q7 on the substrate potential VBB.
Since the source-gate voltage .vertline.V.sub.CS .vertline. of the transistor Q7 is represented by VD-VBB, the lower the reference potential VBB becomes, the lower the ON resistance becomes such that the characteristic curve becomes more sharply-inclined (ex. as for Schottky model, the curve shown in FIG. 6 may be of a quadratic one). The characteristic curve shown in FIG. 7 indicates these matters in respect to the relation between the potential at the node D (Y-axis) and the substrate potential VBB (X-axis). In FIG. 7, same as FIG. 6, as the substrate potential VBB becomes low, the potential at the node D is lowered and the characteristic curve is more sharply-inclined.
Assuming that the pre-set level of the substrate potential VBB is VBBO and that the corresponding potential VD at the node D is VDO (see FIG. 7), VDO is the potential of the node D at which the output EBBG is inverted.
If the threshold voltage .vertline.V.sub.TP .vertline. of the transistor Q8 is fluctuated by .+-..DELTA.V.sub.TP, the potential at the node D and the substrate potential VBB for inverting the output EBBG are given as VDO+.DELTA.V.sub.TP =VD+, and VBBO+.DELTA.VBB+/ .DELTA.VBB-, respectively (see FIG. 7).
That is, the level shift in the detection level of the substrate potential from the pro-set level VBBO by .DELTA.VBB+ or .DELTA.VBB- is caused by the fluctuation .+-..DELTA.V.sub.TP in the threshold voltage .vertline.V.sub.TP .vertline. of the transistor Q8. .DELTA.VBB+ and .DELTA.VBB- denote level shifts of the substrate potential VBB in positive and negative directions respectively.
As shown in FIG. 7, .DELTA.VBB+ is usually greater than .DELTA.VBB-. The circuit simulation for the device adopting the 0.4-.mu.m design rule, indicates that .DELTA.VBB- is 0.15 V and .DELTA.VBB+ is 0.27 V, assuming that VBBO=-1.5 V and .DELTA.V.sub.TP =.+-.0.1 V respectively.
If the potential of the substrate is shifted to higher level direction by a large amount, that is, .DELTA.VBB+ is large, the sub-threshold leakage and the latch-up phenomenon in the cell transistors of the dynamic memory device as well as the latch-up phenomenon or the like in periphery circuit thereof may occur.